1. Field of the Invention
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self Boosting Technique For Non-Volatile Memory;” and U.S. Pat. No. 6,917,542, titled “Detecting Over Programmed Memory,” both patents are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states, an erased state and a programmed state that correspond to data “1” and data “0.” Such a device is referred to as a binary or two-state device.
A multi-state flash memory cell is implemented by identifying multiple, distinct allowed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory cell. Generally, N data bits per memory cell can be represented using 2N threshold voltage ranges, also called data states. Using high number of data bits per memory cell allows producing Flash devices with high data density and thus reduces the overall cost per Flash device. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the memory cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
Typically, the program voltage (Vpgm) is applied to the control gates of the memory cells as a series of pulses. The magnitude of the programming pulses is increased with each successive pulse by a predetermined step size (e.g. 0.2 v, 0.3 v, 0.4 v, or others). During a program operation, a high voltage is applied to the selected word line (WL) and 0 volts is applied to the selected bit line (BL), with the unselected WLs kept at conducting voltage and unselected BLs kept at some voltage that is lower than the programming voltage. A problem arises when it's desired to program one memory cell on a selected WL without programming other memory cells connected to the same word line. Because the program voltage is applied to all memory cells connected to a selected WL, an unselected memory cell (a memory cell that is not to be programmed) on the word line, especially a memory cell adjacent to the memory cell selected for programming, may become inadvertently programmed. The unintentional programming of the unselected memory cell on the selected WL is referred to as “program disturb.” Program disturb is generally worse in the low voltage level memory cells and is increased when using higher programming voltages.
Another problem is the floating gate to floating gate coupling. The floating gate to floating gate coupling phenomena occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored.
The effect of the floating gate to floating gate coupling is of greater concern for multi-state devices because in multi-state devices the allowed threshold voltage ranges and the forbidden ranges are narrower than in binary devices. Therefore, the floating gate to floating gate coupling can result in memory cells being shifted from an allowed threshold voltage range to a forbidden range.
When programming data to multiple states (e.g., rather than binary programming), it is important that the programming process be sufficiently precise so that the read process can unambiguously distinguish between the different threshold voltage distributions. The precision of programming is related to the distribution of threshold voltages of the programmed memory cells subsequent to the programming process. The tighter the threshold voltage distribution, the easier it is to unambiguously read the memory cells. To obtain a tight threshold voltage distribution, many number of programming pulses are used. Using a high number of programming pulses causes a high programming voltage applied to the WL during the program operation, which can cause (in some cases) more program disturb.